As compared to NMOS floating gate (FG) memory cells, PMOS FG memory cells have desirable band-to-band tunneling (BTBT) programming efficiencies. But memory arrays comprised of single transistor PMOS FG memory cells may suffer from problems such as over-erase and BTBT program disturbance, thereby compromising data integrity. As disclosed in commonly-assigned U.S. Pat. No. 5,912,842, the BTBT disturb problem may be solved by constructing memory arrays with two-transistor (2T) PMOS memory cells.
The 2T PMOS memory cell approach has been adapted for integration with CMOS logic processes providing just a single polycrystalline silicon (poly) layer. For example, commonly-assigned U.S. Pat. No. 5,736,764 discloses a variety of 2T PMOS memory cells in which a diffusion region serves as the control plate. To achieve a high density design, the buried diffusion region may be located in the same n-well holding the 2T PMOS cell. It is advantageous to then isolate the buried diffusion region with a P-type layer from the N-well. This isolation requires an additional mask step as well as an additional implantation step.
There are applications, however, wherein a memory array formed using 2T PMOS memory cells need not be pushed to achieve high density. For example, a user may require a nonvolatile memory to store relatively small words such as a radio frequency identification number (RFID). Such a memory need only provide storage for one to two K-bits for typical RFID applications. For such applications, the silicon area occupied by the nonvolatile memory will only be a relatively small portion of that required for the overall integrated circuit. Thus, instead of memory cell size concerns, other concerns may drive the memory design in such applications. For example, a user may desire that no additional mask steps be required other than those already provided for in a standard CMOS logic process, However, as discussed with respect to U.S. Pat. No. 5,736,764, previous single-poly 2T PMOS memory cell designs typically require extra mask steps to form the control plate.
In other applications, a user may allow for the possibility of additional mask steps besides those already provided for in a standard single-poly CMOS logic process so to accomplish higher density designs. However, the silicon area required for the control plate in conventional single-poly 2T PMOS memory cell designs makes a high density single poly design problematic.
Accordingly, there is a need in the art for improved single-poly 2T PMOS memory cell designs compatible with conventional CMOS processes. In addition, there is a need in the art for improved high-density single-poly 2T PMOS memory cell designs.